For producing modern components for high-power electronics and also optoelectronics, the prior art usually uses substrates which can only be fabricated in a very complicated and hence high-cost manner. Furthermore, such substrates often have a high defect density.
An alternative for producing cost-effective and high-quality substrates consists in depositing a thin layer (a few tens of nm) of the desired substrate material on a high-quality and cost-effective substrate, for example, on a silicon wafer. This yields lattice-matched substrates which enable a low-defect epitaxial deposition of further layers.
However, in this method, the substrate determines significant physical properties, in particular the coefficient of thermal expansion. This is problematic because, by way of example, the growth of III-V compound semiconductors such as GaN by means of metal organic chemical vapor deposition (MOCVD) is often effected at comparatively high temperatures of above 1000° C. in order to ensure a sufficient quality for component fabrication. If a layer deposited at such high temperatures is cooled on a substrate having a significantly lower coefficient of thermal expansion, then first a tensile stream of the deposited layer occurs and subsequently the layer often cracks, which renders it unusable.
As proposed in Journal of Crystal Growth 280, 346-351 (2005), N. H. Zhang et al., interlayers of differing composition and/or structure may be used during the deposition, which are intended to compensate for the strains that arise.
One obvious disadvantage is the complicated process implementation, since, in general, different process steps and parameters are necessary for the production of the interlayers as compared to the deposition of the desired layer. In principle, so-called “compliant substrates” or matched substrates constitute another possibility. These are understood to be substrates in which a thin layer of the desired substrate material is applied to another substrate in such a way that there is only a weak mechanical coupling between the substrate and the applied layer.
A method of this type is described for example in Journal of Electronic Materials 29(7), 897-900 (2000), Hobart et al. In this case, first an Si1-xGex layer is deposited on an SOI (“silicon-on-insulator”) wafer, then the buried silicon dioxide layer is doped with boron and phosphorus. This borophosphosilicate layer has the property of being able to flow viscously starting from temperatures of approximately 800° C., which enables a stress relaxation of any layers deposited thereon.
The problem manifested in this case, however, is that deposited layers bulge out on these substrates. The reason for this is due to the high viscosity of the borophosphosilicate layer and the necessity of thermal contraction of the deposited layer when cooling to room temperature. Since the fabrication of modern semiconductor components places high demands on the planarity of the layers, this is a serious disadvantage. Such bulging out has hitherto been possible to be achieved in such material systems only—as described in the above publication—by a patterning of the substrates, which is undesirable in many cases.
Further disadvantages arise from the complexity of the fabrication of such substrates. Use is usually made of SOI (“silicon-on-insulator”) wafers based on technologically complex processes such as the “smart-cut” process or high-dose oxygen ion implantation (“SIMOX” method).
Other methods for fabricating such virtual substrates, as described for example in EP 1437764 A1 and WO2004/082001 A1, deliberately fabricate a defect region in the substrate in order to enable relaxed layers on non-lattice-matched substrates, in particular for the purpose of producing strained silicon layers on relaxed Si1-xGex layers which were grown on silicon.
An ion implantation step is employed here which serves to produce a defect region below the layer already deposited beforehand or a deposited layer system. During a subsequent thermal after-treatment, the defect region leads to the formation of dislocations and stacking faults in the original substrate, which have a relaxing effect on the deposited layer or the layer system. A prerequisite for these methods is thin low-defect layers on the silicon substrate which can relax by means of a thermal after-treatment after the ion implantation step.
The problem in this case, however, is that the defect regions produced remain stable only over short times and anneal with a longer process duration.
This is associated with the fact that Ostwald ripening takes place. That is to say that the cavities coarsen their size distribution by vacancy diffusion and combine to form a small number of larger cavities. As a result, the density of the cavities produced becomes so low that, for energetic reasons, dislocations or stacking faults no longer form between the cavities. This problem occurs in the case of long process times at high temperatures, for example, during the deposition of a layer by means of MOCVD on the layer structure. Since relaxation of the layer structure during cooling is no longer possible on account of the excessively low density of cavities, the deposited layer cracks.
Possibly increasing the cavity density solves this problem only to a limited extent since, starting from a critical density of the cavities, it is possible for the deposited layer to split off—particularly during subsequent high-temperature processes at temperatures greater than or equal to 1000° C.
Therefore, an aspect of the present disclosure is to provide substrates for stress- and crack-free deposition of semiconductor materials and also a method for fabricating substrates of this type.
This aspect of the disclosure involves a method for fabricating a semiconductor layer structure, comprising the following steps: a) provision of a substrate made of a semiconductor material; b) application of a layer made of a second semiconductor material to the substrate for the purpose of producing a semiconductor layer structure; c) implantation of light gas ions into the semiconductor layer structure for the purpose of producing a layer comprising cavities in the semiconductor layer structure; d) stabilization of the cavities by impurity atoms of a specific species; e) application of at least one epitaxial layer to the semiconductor layer structure.
The substrate provided in a) is preferably a wafer made of monocrystalline silicon.
Furthermore, the use of semiconductor wafers fabricated by means of bonding methods is also preferred.
The use of an SOI (“silicon-on-insulator”) wafer as a substrate is likewise preferred.
However, the substrate may also comprise polycrystalline semiconductor material.
The substrate may furthermore also be layer structures comprising a silicon layer, a silicon-germanium (SiGe) layer or a germanium layer.
Generally, all substrates on which monocrystalline or polycrystalline layers can be deposited are suitable.
The layer made of a second semiconductor material that is to be applied in step b) is preferably a monocrystalline silicon carbide layer.
However, a silicon-germanium layer or a layer structure comprising a silicon-germanium layer is also preferred as the layer to be applied in step b).
The application of the layer made of a second semiconductor material for the purpose of producing a semiconductor layer structure in step b) of the method according to this disclosure is preferably effected by means of chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or by ion beam synthesis (IBS).
Depending on the method used for applying the layer in step b), preferred layer thicknesses are 0.5 nm to 100 μm in the case of CVD, 0.5 nm to 5 μm in the case of MBE and 0.5 nm to 1 μm in the case of IBS.
The layer thickness of the layer applied in b) is particularly preferably 1-500 nm, independently of the method used.
In step c) of the method according to this disclosure, light gas ions are implanted into the semiconductor layer structure.
The implantation of the gas ions may be effected in a depth range below an interface between the applied layer and the substrate or else within the layer applied in b).
Here an implantation energy is chosen in the first case such that the cavities arise just below an interface between the substrate and applied layer, that is to say preferably within the range of 0-500 nm below that interface.
By means of the implantation of light gas ions, cavities or bubbles are produced in the semiconductor layer structure.
The implanted gas ions are preferably hydrogen ions.
Implantation of noble gas ions of one or more atom types selected from a group of helium ion, neon ions and argon ions is also preferred.
The implantation of noble gas ions may also be an implantation of mixtures of the atom types or else a combination of separate implantations of the atom types.
By way of example, it is possible, therefore, to combine a helium ion implantation with a neon ion implantation.
On the other hand, a combination of an implantation of hydrogen ions and an implantation of noble gas ions of one or more atom types selected from a group of helium ions, neon ions and argon ions is also preferred.
By way of example it is possible, therefore, to combine an implantation of hydrogen ions with an implantation of helium ions.
For example, for a 70 nm thick SiC layer on a silicon substrate, an implantation energy of 22 keV for helium ions and a dose of approximately 2×1016 cm−2 may be chosen. This then leads to a defect region of approximately 0-70 nm below the interface between the applied layer and the substrate.
Lower implantation energies can be chosen in order to produce the defect region within the applied layer.
The implantation energies, depending on the thickness and type of the deposited layer, preferably lie within the range of 1 keV-2 MeV.
The implantation energies particularly preferably lie within the range of 10-200 keV.
In particular, implantation energies of 20-50 keV are especially to be preferred.
The point in time at which the cavities arise can be controlled by way of the choice of the implantation temperature:
If low implantation temperatures and high doses are chosen, cavities having a certain size are already produced directly after the implantation.
It is believed to be preferable, however, to choose higher implantation temperatures of approximately 400° C. The foremost aspect of such a temperature is to produce only seeds for cavities, which, after suitable stabilization thereof by impurity atoms, even during subsequent long, high-temperature processes at temperatures of 900-1250° C. and with treatment durations of 2 hours or longer, result in a narrow cavity distribution with average cavity diameters of approximately 10 nm.
In particular, it is possible to prevent the layer from splitting off later in a high-temperature process up to a temperature of 1250° C.
The choice of the doses of the hydrogen or noble gas ions to be implanted is dependent on the type and thickness of the applied layer and also on the implantation energy.
The doses of the hydrogen and/or noble gas ions to be implanted preferably lie within the range of 1×1013 to 1×1017 cm−2.
Doses within the range of 1×1015 cm−2 to 5×1016 cm−2 are particularly preferred.
It will be understood by the person skilled in the art that the resulting concentrations of impurity atoms are dependent on the implanted dose and on the thermal out-diffusion. The required doses are therefore preferably determined experimentally.
A tilting of the semiconductor layer structure relative to the ion beam during the implantation is likewise preferred.
The semiconductor layer structure is preferably tilted by an angle of 0-60° with respect to the ion beam.
Angles of 0-30° are particularly to be preferred, angles of 0-15° being especially preferred.
In step d) of the method according to the disclosure, the cavities in the semiconductor layer structure are stabilized by impurity atoms of one or more atom types selected from a group of oxygen, nitrogen and carbon.
This is effected, in the case where impurity atoms of those atom types are already present in the substrate and/or in the applied layer, at least in the region of the layer comprising cavities, preferably by means of a thermal treatment of the semiconductor layer structure conducted at a temperature of 600° C. or greater.
In this case, the impurity atoms may be present in dissolved form, in the form of compounds with the substrate material, or as precipitates.
A separate thermal treatment is not necessary, however, nor is it preferred if the application of the at least one epitaxial layer in accordance with step e) is effected at a temperature of at least 600° C.
Sufficient densities of areal defects such as are required for a relaxation of the deposited layer are not achieved below said temperature.
A thermal treatment of the semiconductor layer structure at very high temperatures of 1300° C. or higher is possible, in principle. However, the dynamic behavior of Ostwald ripening must be taken into consideration here, which may lead to undesirable effects at such temperatures, even in the case of impurity-atom-stabilized cavities. It is primarily desirable to prevent the applied layer from chipping off, and also an excessively large decrease in the density of the cavities on account of coarsening. Therefore, the thermal treatment of the semiconductor layer structure and the deposition of epitaxial layers on the semiconductor layer structure are preferably effected at temperatures of 600-1250° C.
If impurity atoms of one or more atom types, which are preferably selected from a group of nitrogen, oxygen and carbon, are not present in sufficient concentration in the substrate or at least in the region of the cavities produced, an implantation of ions of said atom types into the semiconductor layer structure is preferably effected in step d).
In this case, the implantation is preferably chosen such that the concentration maximum of the impurity atoms and the concentration maximum of the implanted gas ions coincide or at least lie in a similar depth range.
Therefore, implantation energies of 10-200 keV are preferably chosen.
Finally, in accordance with step e) at least one epitaxial layer is applied to the semiconductor layer structure.
At least one epitaxial layer is preferably a layer made of monocrystalline silicon.
The at least one epitaxial layer preferably comprises a nitride compound semiconductor.
The at least one epitaxial layer preferably comprises semiconductor material having a significantly different, namely higher, coefficient of thermal expansion in comparison with the semiconductor material of the substrate.
By way of example, all the compound semiconductors have a substantially different, namely a greater, coefficient of thermal expansion in comparison with silicon, cf. Table 1.
The deposited layers are typically II-IV and III-V compound semiconductors. In particular, they are layers composed of: AlxGa1-xN, AlxGayIn1-x-yN, AlxGayIn1-x-yP, AlxGa1-xSb, AlxGayIn1-x-yNaSb1-a, AlxGayIn1-x-yNaPbSb1-a-b, GaAs, ZnO, CdTe, CdS, CdSe and CdSxSe1-x.
In particular, layer stacks as a combination of the above compound semiconductors are also conceivable and preferred.
TABLE 1Coefficients of thermal expansion forselected semiconductor materialsCoeff. of lin.Coeff. of lin.Coeff. of lin.thermalthermalthermalMaterialexpansionexpansionexpansionSi2.6GaN5.593.173C—SiC3.86H—SiC4.34.7ZnO6.513.02A1N4.155.27
In this case, these layers may, of course, be doped with impurity atoms of any desired type according to their intended application.
Depending on the desired orientation or crystal structure (100)-, (110)-, (111)- or else misoriented semiconductor wafers may be used in the case where silicon is used as substrate.
If the semiconductor layer structure is a silicon carbide layer on a silicon wafer, the deposition of nitride compound semiconductors and thus the fabrication of starting materials for applications in optoelectronics are preferred.
In this case, the silicon carbide layer is preferably between 1 nm and 500 nm thick.
The layer thickness particularly preferably lies within the range of 30 nm to 150 nm, layer thicknesses of between 50 nm and 100 nm being especially preferred.
The thickness of the deposited nitride layer preferably lies—according to the later application—within the range of 100 nm to 100 μm, layer thicknesses within the range of 200 nm to 20 μm being particularly preferred and layers having thickness of between 500 nm and 5 μm being especially preferred.
If a layer structure made of GaN/AlN on a silicon carbide layer on silicon is involved, then it is possible to achieve threading dislocation densities of less than or equal to 1010 cm−2, preferably within the range of 106 to 1010 cm−2.
Another aspect of the disclosure involves a semiconductor layer structure, comprising a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated. Furthermore a region enriched with impurity atoms is situated either in the layer made of a second semiconductor material or at a specific depth below the interface between the layer made of a second semiconductor material and the substrate. Additionally a layer within the region enriched with impurity atoms comprises cavities produced by ion implantation. Furthermore at least one epitaxial layer is applied to the layer made of a second semiconductor material. Also a defect region comprising dislocations and stacking faults lies within the layer comprising cavities. The at least one epitaxial layer is largely crack-free, and a residual strain of the at least one epitaxial layer is less than or equal to 1 GPa.